1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit and a recorded data reproduction apparatus which utilizes the PLL circuit.
2. Description of the Related Art
According to a conventional magnetic disk drive apparatus such as HDD, normally, a data signal read out from the disk is initially quantized using an A/D (analog to digital) converter, and then the quantized data signal is subject to the digital signal processing so that a phase error is detected from the digital signal. Then, the detected error is fed back to the AID converter in order to execute phase locking.
FIG. 6 exemplifies a phase-locked loop circuit built in a conventional magnetic disk drive apparatus. According to this phase-locked loop circuit shown in FIG. 6, after being read out from a magnetic disk, an analog data signal is initially equalized by an analog filter (not shown), which is then quantized by an A/D converter 101 and then optimally equalized by an FIR (Finite Impulse Response) filter 102, and finally, a phase error is detected by digital arithmetic operation of a phase-detector 103.
Next, the detected phase-error data signal is converted into an analog data signal using D/A (digital to analog) converter 104, and then, the analog data signal is delivered to a VCO (voltage-controlled oscillator) 106 through a loop filter 105 as voltage for controlling its oscillation. A clock signal oscillated by the VCO 106 is delivered to the A/D converter 101 as its own sampling clock signal.
Nevertheless, when operating the above-cited phase-locked loop circuit, depending on a tap number of the FIR filter 102, delay corresponding to a minimum of three (3) through five (5) clock cycles is generated. Further, in order to execute an arithmetic operation for detecting a phase error, still further duration corresponding to several clock cycles is required. Because of this, loss time in the phase-locked loop expands. Inasmuch as oscillation is apt to be generated when increasing loop-gain, loop-gain can hardly be raised.
As a means for solving the problem, such a method is conceivable, which detects a phase error from an equalized data signal before delivery to the FIR filter 102. However, even in this case, since a data signal output from the A/D converter 101 delays one or more clock cycles against the sampling timing, it results in the generation of loop-delay by one to several clock cycles.
FIG. 7 shows an example of a phase-locked loop circuit built in a tape drive apparatus. In FIG. 7, after being read out from a magnetic tape, an analog signal being equalized by an analog filter (not shown) is then quantized by an A/D converter 201, and then the quantized analog signal is optimally equalized by an FIR (Finite Impulse Response) filter 202. On the other hand, a pulse detector 203 executes comparison between the analog signal to be delivered to the A/D converter 201 and a proper threshold value, and then converts the analog signal into a pulse signal.
Simultaneously, a phase-comparator 204 compares a phase of the pulse signal with a phase of the pulse output from a voltage-controlled oscillator VCO 206, and then delivers the phase-difference data to the VCO 206 through a loop filter 205 as the voltage for controlling its oscillation. A clock signal,oscillated by the VCO 206 is delayed by a clock-delay circuit 207 and then delivered to the A/D converter 201 as its own sampling clock signal.
Concretely, according to the above-referred phase-locked loop circuit shown in FIG. 7, by causing the phase of the pulse output from the VCO 206 to be locked with the phase of the pulse signal output from the pulse detector 203, loss time of the PLL (Phase-Locked Loop) is eliminated. Nevertheless, when operating this conventional phase-locked loop circuit based on a pulse-detection system, in order to optimize sampling timing of the A/D converter 201, it was necessary to properly adjust timing by inserting the clock delay circuit 207.
The invention has been realized in consideration of the above technical problem to solve. The object of the invention is to provide a novel PLL (Phase-Locked Loop) circuit which is capable of minimizing loss time of the loop and enhancing loop gain without necessarily adjusting timing of sampling clock of an AID converter, while the invention also provides a recorded-data reproduction apparatus utilizing the novel PLL circuit.
According to the present invention, a PLL (Phase-Locked Loop) circuit comprises an A/D converter which quantizes an input signal substantially being equalized into a waveform conforming to a partial-response (PR) system; and a phase-error detection circuit including a pattern detector which detects a pattern of the waveform of the signal being input to the A/D converter, and then, based on a result of the detection by the pattern detector, extracts an phase error from the data output from the A/D converter, in which the PLL circuit executes phase locking by causing a phase-error output from the phase-error detection circuit to be fed back to the A/D converter. The PLL circuit is utilized in a recorded data reproduction apparatus for reproducing a magnetic disk or an optical disk, as a phase-locked loop circuit for executing phase locking so that a phase difference between a sampling clock of the A/D converter for quantizing the input signal substantially equalized into the waveform of the partial response system and the input signal becomes zero (0).
In the PLL circuit and the recorded data reproducing apparatus utilizing the PLL circuit constructed as described above, a waveform pattern of the input signal to the A/D converter is detected by the pattern detector, and a phase error is extracted from the data output from the A/D converter in accordance with the detection result. The extracted phase error data is, for example, integrated by a loop filter, so as to be given to a voltage control oscillator as a control voltage. The oscillation clock of the voltage control oscillator is used as a sampling clock of the AID converter.